MC9S12C128V1 Datasheet, PDF (118/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 3 Module Mapping Control (MMCV4) Block Description
3.3.2.7 Memory Size Register 0 (MEMSIZ0)
Module Base + 0x001C
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R REG_SW0
0
EEP_SW1 EEP_SW0
0
RAM_SW2 RAM_SW1 RAM_SW0
W
Reset
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 3-9. Memory Size Register 0 (MEMSIZ0)
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Table 3-7. MEMSIZ0 Field Descriptions
Field
Description
7
REG_SW0
Allocated System Register Space
0 Allocated system register space size is 1K byte
1 Allocated system register space size is 2K byte
5:4
Allocated System EEPROM Memory Space — The allocated system EEPROM memory space size is as
EEP_SW[1:0] given in Table 3-8.
2
Allocated System RAM Memory Space — The allocated system RAM memory space size is as given in
RAM_SW[2:0] Table 3-9.
Table 3-8. Allocated EEPROM Memory Space
eep_sw1:eep_sw0
00
01
10
11
Allocated EEPROM Space
0K byte
2K bytes
4K bytes
8K bytes
ram_sw2:ram_sw0
000
001
010
Table 3-9. Allocated RAM Memory Space
Allocated
RAM Space
2K bytes
4K bytes
6K bytes
RAM
Mappable Region
2K bytes
4K bytes
8K bytes⁽²⁾
INITRM
Bits Used
RAM[15:11]
RAM[15:12]
RAM[15:13]
RAM Reset
Base Address⁽¹⁾
0x0800
0x0000
0x0800
118
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24