MC9S12C128V1 Datasheet, PDF (374/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
12.4.1.3 Clock Select
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock
choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock
selection is done with the PCLKx control bits in the PWMCLK register.
NOTE
Changing clock control bits while channels are operating can cause
irregularities in the PWM outputs.
12.4.2 PWM Channel Timers
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period
register and a duty register (each are 8 bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by a match between the duty register
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis. Figure 12-35 shows a block diagram for PWM timer.
Clock Source
GATE
(clock edge sync)
8-Bit Counter
PWMCNTx
From Port PWMP
Data Register
up/down reset
8-Bit Compare =
PWMDTYx
8-Bit Compare =
PWMPERx
T
Q
M
U
Q^X
R
M
U
X _{To Pin}
Driver
PPOLx
PWMEx
374
QT
Q
R
CAEx
Figure 12-35. PWM Timer Channel Block Diagram
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Freescale Semiconductor