MC9S12C128V1 Datasheet, PDF (86/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.2.3 Port S Data Direction Register (DDRS)
Module Base + 0x000A
7
R
0
W
Reset
0
Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
0
0
DDRS3
DDRS2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-12. Port S Data Direction Register (DDRS)
Table 2-11. DDRS Field Descriptions
1
DDRS1
0
0
DDRS0
0
Field
Description
3–0
DDRS[3:0]
Direction Register Port S — This register configures each port S pin as either input or output.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is
forced to be an output if the SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel
is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS
or PTIS registers, when changing the DDRS register.
86
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24