MC9S12C128V1 Datasheet, PDF (206/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 7 Debug Module (DBGV1) Block Description
Table 7-14. DBGC2 Field Descriptions (continued)
Field
4
TAGAB
3
BKCEN
2
TAGC
1
RWCEN
0
RWC
Description
Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Breakpoint Comparator C Enable Bit — This bit enables the breakpoint capability using comparator C.
0 Comparator C disabled for breakpoint
1 Comparator C enabled for breakpoint
Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode.
Comparator C Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for comparator C. RWCEN is not useful for tagged breakpoints.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
7.3.2.8 Debug Control Register 3 (DBGC3)
Module Base + 0x0029
Starting address location affected by INITRG register setting.
7
R
BKAMBH⁽¹⁾
W
6
BKAMBL¹
5
BKBMBH⁽²⁾
4
BKBMBL²
3
RWAEN
2
RWA
Reset
0
0
0
0
0
0
1. In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s.
2. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
Figure 7-14. Debug Control Register 3 (DBGC3)
1
RWBEN
0
0
RWB
0
206
MC9S12C-Family / MC9S12GC-Family
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Rev 01.24