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MC9S12C128V1 Datasheet, PDF (300/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV2)
Table 10-9. CANRFLG Register Field Descriptions
Field
Description
7
WUPIF
Wake-Up Interrupt Flag â If the MSCAN detects CAN bus activity while in sleep mode (see Section 10.4.5.4,
âMSCAN Sleep Mode,â) and WUPE = 1 in CANTCTL0 (see Section 10.3.2.1, âMSCAN Control Register 0
(CANCTL0)â), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ï¬ag is set.
0 No wake-up activity observed while in sleep mode
1 MSCAN detected activity on the CAN bus and requested wake-up
6
CSCIF
CAN Status Change Interrupt Flag â This ï¬ag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-
bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system
on the actual CAN bus status (see Section 10.3.2.6, âMSCAN Receiver Interrupt Enable Register (CANRIER)â).
If not masked, an error interrupt is pending while this ï¬ag is set. CSCIF provides a blocking interrupt. That
guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change
interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause
an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt
is cleared again.
0 No change in CAN bus status occurred since last interrupt
1 MSCAN changed current CAN bus status
5:4
RSTAT[1:0]
Receiver Status Bits â The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt ï¬ag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00 RxOK: 0 ⤠receive error counter ⤠96
01 RxWRN: 96 < receive error counter ⤠127
10 RxERR: 127 < receive error counter
11 Bus-off(1): transmit error counter > 255
3:2
TSTAT[1:0]
Transmitter Status Bits â The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt ï¬ag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00 TxOK: 0 ⤠transmit error counter ⤠96
01 TxWRN: 96 < transmit error counter ⤠127
10 TxERR: 127 < transmit error counter ⤠255
11 Bus-Off: transmit error counter > 255
1
OVRIF
Overrun Interrupt Flag â This ï¬ag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this ï¬ag is set.
0 No data overrun condition
1 A data overrun detected
0
Receive Buffer Full Flag â RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This
RXF(2) ï¬ag indicates whether the shifted buffer is loaded with a correctly received message (matching identiï¬er,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF ï¬ag must be cleared to release the buffer. A set RXF ï¬ag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this ï¬ag is set.
0 No new message available within the RxFG
1 The receiver FIFO is not empty. A new message is available in the RxFG
1. Redundant Information for the most critical CAN bus status which is âbus-offâ. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
2. To ensure data integrity, do not read the receive buffer registers while the RXF ï¬ag is cleared. For MCUs with dual CPUs,
reading the receive buffer registers while the RXF ï¬ag is cleared may result in a CPU fault condition.
300
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
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