MC9S12C128V1 Datasheet, PDF (320/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Module Base + 0x00X3
7
6
5
4
3
2
1
0
R
W
Reset:
x
x
x
x
x
x
x
x
= Unused; always read ‘x’
Figure 10-32. Identifier Register 3 — Standard Mapping
10.3.3.2 Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x0004 (DSR0)
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
7
R
DB7
W
6
DB6
5
DB5
4
DB4
3
DB3
2
DB2
1
DB1
0
DB0
Reset:
x
x
x
x
x
x
x
x
Figure 10-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Field
7:0
DB[7:0]
Table 10-30. DSR0–DSR7 Register Field Descriptions
Data bits 7:0
Description
320
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24