MC9S12C128V1 Datasheet, PDF (122/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 3 Module Mapping Control (MMCV4) Block Description
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3.4 Functional Description
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding
and select signal generation, memory expansion, and security decoding for the system. Each aspect is
described in the following subsections.
3.4.1 Bus Control
The MMC controls the address bus and data buses that interface the core with the rest of the system. This
includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages
all CPU read data bus swapping operations.
3.4.2 Address Decoding
As data flows on the core address bus, the MMC decodes the address information, determines whether the
internal core register or firmware space, the peripheral space or a memory register or array space is being
addressed and generates the correct select signal. This decoding operation also interprets the mode of
operation of the system and the state of the mapping control registers in order to generate the proper select.
The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip
select (XCS).
3.4.2.1 Select Priority and Mode Considerations
Although internal resources such as control registers and on-chip memory have default addresses, each can
be relocated by changing the default values in control registers. Normally, I/O addresses, control registers,
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MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24