MC9S12C128V1 Datasheet, PDF (201/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

7.3.2.3
Chapter 7 Debug Module (DBGV1) Block Description
Debug Trace Buffer Register (DBGTB)
Module Base + 0x0022
Starting address location affected by INITRG register setting.
R
W
Reset
15
Bit 15
u
14
Bit 14
13
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
u
u
u
u
u
= Unimplemented or Reserved
Figure 7-6. Debug Trace Buffer Register High (DBGTBH)
9
Bit 9
u
8
Bit 8
u
Module Base + 0x0023
Starting address location affected by INITRG register setting.
7
R Bit 7
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
Figure 7-7. Debug Trace Buffer Register Low (DBGTBL)
Table 7-7. DBGTB Field Descriptions
Field
15:0
Description
Trace Buffer Data Bits — The trace buffer data bits contain the data of the trace buffer. This register can be read
only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the
trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the
debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same
capture mode bit settings as when the trace buffer data was recorded (See Section 7.4.2.9, “Reading Data from
Trace Buffer”). Because reads will reflect the contents of the trace buffer RAM, the reset state is undefined.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
201
Rev 01.24