MC9S12C128V1 Datasheet, PDF (664/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Appendix A Electrical Characteristics
A.4.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.4.1.4 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.4.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
A.4.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. In Pseudo Stop Mode the voltage regulator is switched to reduced performance mode to
reduce power consumption. The returning out of pseudo stop to full performance takes t_vup. The controller
can be woken up by internal or external interrupts.After t_wrs in Wait or t_vup + t_wrs in Pseudo Stop the CPU
starts fetching the interrupt vector.
A.4.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t_CQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t_UPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequency of the incoming clock signal is below the Assert Frequency f_CMFA.
664
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24