MC9S12C128V1 Datasheet, PDF (204/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 7 Debug Module (DBGV1) Block Description
PAGSEL
7
6
DBGCXX
DBGCXH[15:12]
EXTCMP
0
5
0
4
3
2
BIT 15 BIT 14 BIT 13 BIT 12
1
BIT 0
SEE NOTE 1
PORTK/XAB
XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11.
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 7-10. Comparator C Extended Comparison in BKP/DBG Mode
7.3.2.6 Debug Comparator C Register (DBGCC)
Module Base + 0x0026
Starting address location affected by INITRG register setting.
R
W
Reset
15
Bit 15
0
14
Bit 14
13
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
9
Bit 9
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-11. Debug Comparator C Register High (DBGCCH)
Module Base + 0x0027
Starting address location affected by INITRG register setting.
7
R Bit 7
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-12. Debug Comparator C Register Low (DBGCCL)
8
Bit 8
0
0
Bit 0
0
204
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24