MC9S12C128V1 Datasheet, PDF (80/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2 Register Descriptions
Table 2-2 summarizes the effect on the various configuration bits — data direction (DDR), input/output
level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Table 2-2. Pin Configuration Summary
DDR IO RDR PE PS IE⁽¹⁾
0
X
X
0
X
0
0
X
X
1
0
0
0
X
X
1
1
0
0
X
X
0
0
1
0
X
X
0
1
1
0
X
X
1
0
1
0
X
X
1
1
1
1
0
0
X
X
0
1
1
0
X
X
0
1
0
1
X
X
0
1
1
1
X
X
0
1
0
0
X
0
1
1
1
0
X
1
1
1
0
1
X
0
1
1
1
1
X
1
1
1. Applicable only on ports P and J.
Function
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Pull Device
Disabled
Pull up
Pull down
Disabled
Disabled
Pull up
Pull down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
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MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24