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MC9S12C128V1 Datasheet, PDF (192/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual | |||
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Chapter 7 Debug Module (DBGV1) Block Description
The DBG in DBG mode includes these distinctive features:
⢠Three comparators (A, B, and C)
â Dual mode, comparators A and B used to compare addresses
â Full mode, comparator A compares address and comparator B compares data
â Can be used as trigger and/or breakpoint
â Comparator C used in LOOP1 capture mode or as additional breakpoint
⢠Four capture modes
â Normal mode, change-of-ï¬ow information is captured based on trigger speciï¬cation
â Loop1 mode, comparator C is dynamically updated to prevent redundant change-of-ï¬ow
storage.
â Detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are
stored in trace buffer
â Proï¬le mode, last instruction address executed by CPU is returned when trace buffer address is
read
⢠Two types of breakpoint or debug triggers
â Break just before a speciï¬c instruction will begin execution (tag)
â Break on the ï¬rst instruction boundary after a match occurs (force)
⢠BDM or SWI breakpoint
â Enter BDM on breakpoint (BDM)
â Execute SWI on breakpoint (SWI)
⢠Nine trigger modes for comparators A and B
âA
â A or B
â A then B
â A and B, where B is data (full mode)
â A and not B, where B is data (full mode)
â Event only B, store data
â A then event only B, store data
â Inside range, A ⤠address ⤠B
â Outside range, address < Î or address > B
⢠Comparator C provides an additional tag or force breakpoint when capture mode is not conï¬gured
in LOOP1 mode.
⢠Sixty-four word (16 bits wide) trace buffer for storing change-of-ï¬ow information, event only data
and other bus information.
â Source address of taken conditional branches (long, short, bit-conditional, and loop constructs)
â Destination address of indexed JMP, JSR, and CALL instruction.
â Destination address of RTI, RTS, and RTC instructions
â Vector address of interrupts, except for SWI and BDM vectors
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MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
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