MC9S12C128V1 Datasheet, PDF (646/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1)
21.4.4 Flash Reset Sequence
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash array memory according to Table 21-1:
• FPROT — Flash Protection Register (see Section 21.3.2.5)
• FSEC — Flash Security Register (see Section 21.3.2.2)
21.4.4.1 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/array being erased is not guaranteed.
21.4.5 Interrupts
The Flash module can generate an interrupt when all Flash commands have completed execution or the
Flash address, data, and command buffers are empty.
Table 21-17. Flash Interrupt Sources
Interrupt Source
Flash Address, Data, and Command
Buffers are empty
All Flash commands have completed
execution
Interrupt Flag
CBEIF
(FSTAT register)
CCIF
(FSTAT register)
Local Enable
CBEIE
CCIE
Global (CCR) Mask
I Bit
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
21.4.5.1 Description of Interrupt Operation
Figure 21-26 shows the logic used for generating interrupts.
The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the generation of interrupts.
CBEIF
CBEIE
FLASH INTERRUPT REQUEST
CCIF
CCIE
Figure 21-26. Flash Interrupt Implementation
For a detailed description of these register bits, refer to Section 21.3.2.4, “Flash Configuration Register
(FCNFG)” and Section 21.3.2.6, “Flash Status Register (FSTAT)”.
646
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24