MC68HC11PH8 Datasheet, PDF (90/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

4.10.1 OPT2 — System configuration options register 2
System conÞg. options 2 (OPT2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0038 LIRDV CWOM STRCH IRVNE LSBF SPR2 EXT4X DISE x00x 0000
LIRDV — LIR driven (refer to Section 3)
4
1 (set) – Enable LIR push-pull drive.
0 (clear) – LIR not driven on MODA/LIR pin.
CWOM — Port C wired-OR mode
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
STRCH — Stretch external accesses (refer to Section 3)
1 (set) – Off-chip accesses are extended by one E clock cycle.
0 (clear) – Normal operation.
IRVNE — Internal read visibility/not E (refer to Section 3)
1 (set) – Data from internal reads is driven out of the external data bus.
0 (clear) – No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set) – E pin is driven low.
0 (clear) – E clock is driven out from the chip.
LSBF — LSB first enable (refer to Section 7)
1 (set) – SPI1 data is transferred LSB first.
0 (clear) – SPI1 data is transferred MSB first.
SPR2 — SPI1 clock rate select (refer to Section 7)
EXT4X — 4XLCK or EXTAL clock output select (refer to Section 3
1 (set) – EXTALi clock output on the 4XOUT pin.
0 (clear) – 4XCLK clock output on the 4XOUT pin.
MOTOROLA
4-12
PARALLEL INPUT/OUTPUT
TPG
MC68HC11PH8