MC68HC11PH8 Datasheet, PDF (153/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.5 Real-time interrupt
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate,
has two possible clock sources. When the PLL clock generation is not used (VDDSYN low), the
RTI function is clocked by the 16-bit free-running counter (ST4XCK/2¹⁵). When the PLL clock
generation is used (VDDSYN high), the RTI clock source is the underflow of the 8-bit modulus
timer A (CLK64). This ensures that the RTI interrupt rate is unaffected by changes made to the
bus speed by the PLL circuit. See Figure 8-1 and Figure 8-2. The RTI clock rate is controlled and
configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The
different rates available are a product of the source frequency and the value of bits RTR[1:0]. If
VDDSYN is low, the source frequency, ST4XCK/2¹⁵, can be divided by 1,2,4 or 8. If VDDSYN is
high, the source frequency, CLK64, can be divided by 1,2,4 or 64. Refer to Table 8-2 and Table
8-3 which show examples of periodic real-time interrupt rates. The RTII bit in the TMSK2 register
enables the interrupt capability.
Table 8-2 RTI periodic rates (PLL disabled)
RTR[1:0] ST4XCK = 12MHz ST4XCK = 8MHz ST4XCK = 4MHz ST4XCK = xMHz
00
2.731 ms
4.096 ms
8.192 ms
2¹⁵/ST4XCK
01
5.461 ms
8.192 ms
16.384 ms
2¹⁶/ST4XCK
10
10.923 ms
16.384 ms
32.768 ms
2¹⁷/ST4XCK
11
21.845 ms
32.768 ms
65.536 ms
2¹⁸/ST4XCK
8
Table 8-3 RTI periodic rates (PLL enabled)
RTR[1:0]
00
01
10
11
EXTALi = 640kHz
0.4 ms
0.8 ms
1.6 ms
25.6 ms
EXTALi = 32.768kHz
7.81 ms
15.63 ms
31.25 ms
500 ms
EXTALi = 32kHz
8.0 ms
16.0 ms
32.0 ms
512 ms
EXTALi = xkHz
2⁸/EXTALi
2⁹/EXTALi
2¹⁰/EXTALi
2¹⁴/EXTALi
Note:
The values in Table 8-3 assume that the 8-bit modulus timer is loaded to give an
EXTALi/2⁸ prescaler value. Other prescaler values are possible, in the range EXTALi/4
to EXTALi/4080 (see Section 8.3.1).
Either clock source causes the time between successive RTI timeouts to be a constant that is
independent of the software latency associated with flag clearing and service. For this reason, an
RTI period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is
generated. After reset, one entire RTI period elapses before the RTIF flag is set for the first time.
Refer to the TMSK2, TFLG2, and PACTL registers.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-19