MC68HC11PH8 Datasheet, PDF (165/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.2.3
PWPOL — PWM timer polarity & clock source select register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Pulse width polarity select (PWPOL) $0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
PCLK[4:3] — Pulse width channel 4/3 clock select
1 (set) – Clock S is source.
0 (clear) – Clock B is source.
PCLK[2:1] — Pulse width channel 2/1 clock select
1 (set) – Clock S is source.
0 (clear) – Clock A is source.
PPOL[4:1] — Pulse width channel x polarity
1 (set) – PWM channel x output is high at the beginning of the clock cycle and
goes low when duty count is reached.
0 (clear) – PWM channel x output is low at the beginning of the clock cycle and
goes high when duty count is reached.
Each channel has a polarity bit that allows a cycle to start with either a high or a low level. This is
8
shown on the block diagram, Figure 8-5, as a selection of either the Q output or the Q output of the
PWM output flip flop. When one of the bits in the PWPOL register is set, the associated PWM channel
output is high at the beginning of the clock cycle, then goes low when the duty count is reached.
8.2.4 PWSCAL — PWM timer prescaler register
Pulse width scale (PWSCAL)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0062 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result
by two. If PWSCAL = $00, clock A is divided by 256, then divided by two to generate clock S.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-31