MC68HC11PH8 Datasheet, PDF (194/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.2.10 Serial peripheral interface (SPI)
The SPI1 and SPI2 systems are disabled by reset. Their associated port pins default to being
general purpose I/O lines.
10.2.11 Analog-to-digital converter
The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared by reset,
which disables the A/D system. The conversion complete flag is cleared by reset.
10.2.12 LCD module
The LCD module is disabled by reset. PB4-PB7 default to being general purpose I/O lines in single
chip mode, or higher order address outputs in expanded mode.
10.2.13 System
The EEPROM programming controls are disabled, so the memory system is configured for normal
read operation. PSEL[4:0] are initialized with the binary value %00110, causing the external IRQ
pin to have the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation
(for wired-OR systems). The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status
of the MODB and MODA inputs at the rising edge of reset. The DLY control bit is set to specify that
an oscillator start-up delay is imposed upon recovery from STOP mode or power-on reset. The
clock monitor system is disabled because CME and FCME are cleared.
10
MOTOROLA
10-10
RESETS AND INTERRUPTS
TPG
MC68HC11PH8