MC68HC11PH8 Datasheet, PDF (122/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

NF2 — Noise error flag 2
1 (set) – Noise detected.
0 (clear) – No noise detected.
This bit is set when noise is detected on the receive line during an MI BUS pull field.
6.6.6 S2SR2 — MI BUS2 status register 2
SCI/MI 2 status 2 (S2SR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0055 0
0
0
0
0
0
0 RAF2 0000 0000
RAF2 — Receiver active flag (read only)
6
1 (set) – A character is being received.
0 (clear) – A character is not being received.
6.6.7 S2DRL — MI BUS2 data register
SCI/MI 2 data low (S2DRL)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undeÞned
0
1
0
1 S1 S2 S3 1 Pull Þeld
A2 A1 A0 D4 D3 D2 D1 D0 Push Þeld
This register forms the 8-bit data/address word for the MI push field and contains the 3-bit data
word received as the MI pull field.
R/T[7:0] — Receiver/transmitter data bits [7:0]
READ: Reads access the three bits of pull field data (stored in bits 3–1) of the read-only MI BUS
receive data register. Bits [7:4, 0] are a fixed data pattern when a valid status and end-of-frame is
returned. A valid status is represented by the following data pattern: 0101 xxx1 (bits 7–0), where
‘xxx’ is the status. All ones in the receive data register indicate that an error occurred on the
MI BUS. Bits are received LSB first by the MCU, and the status bits map as shown in the above
table.
WRITE: Writes access the eight bits of the write-only MI BUS transmit data register. MI BUS
devices require a 5-bit data pattern followed by a 3-bit address pattern to be sent during the push
field. The data pattern is mapped to the lowest five bits of the data register and the address to the
highest three bits, as shown in the above table. Thus MI-data[4:0] is written to S2DRL[4:0] and
MI-address[2:0] is written to S2DRL[7:5].
MOTOROLA
6-12
MOTOROLA INTERCONNECT BUS (MI BUS)
TPG
MC68HC11PH8