MC68HC11PH8 Datasheet, PDF (129/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure
7-2 and Section 7.2.1.
SPR1 and SPR0 — SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 7-1. Note that SPR2 is located in the
OPT2 register, and that its state on reset is zero.
Table 7-1 SPI clock rates
SPR[2:0]
E clock
divide ratio
SPI clock frequency (≡ baud rate) for:
E = 2MHz E = 3MHz E = 4MHz
000
2
1.0 MHz
1.5 MHz
2.0 MHz
001
4
500 kHz
750kHz
1.0 MHz
010
16
125 kHz 187.5 kHz 250 kHz
011
32
62.5 kHz
93.7 kHz
125 kHz
100
8
250 kHz
375 kHz
500 kHz
7
101
16
125 kHz 187.5 kHz 250 kHz
110
64
31.3 kHz 46.9 kHz 62.5 kHz
111
128
15.6 kHz 23.4 kHz 31.3 kHz
7.5.2 SPSR — SPI status register
SPI status (SPSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0029 SPIF WCOL 0 MODF 0
0
0
0 0000 0000
SPIF — SPI interrupt complete flag
1 (set) – Data transfer to external device has been completed.
0 (clear) – No valid completion of data transfer.
SPIF is set upon completion of data transfer between the processor and the external device. If
SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit,
read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first,
attempts to write SPDR are inhibited.
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-7