MC68HC11PH8 Datasheet, PDF (166/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.2.5 PWEN — PWM timer enable register
Pulse width enable (PWEN)
Address bit 7 bit 6 bit 5
$0063 TPWSL DISCP 0
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0 PWEN4 PWEN3 PWEN2 PWEN1 0000 0000
Each timer has an enable bit to start its waveform output. Writing any of these PWENx bits to one
causes the associated port line to become an output regardless of the state of the associated DDR
bit. This does not change the state of the DDR bit and when PWENx returns to zero the DDR bit
again controls I/O state. On the front end of the PWM timer the clock is connected to the PWM
circuit by the PWENx enable bit being high. There is a synchronizing circuit to guarantee that the
clock will only be enabled or disabled at an edge.
PWEN contains 4 PWM enable bits — one for each channel. When an enable bit is set to one, the
pulse modulated signal becomes available at the associated port pin.
TPWSL — PWM scaled clock test bit (Test mode only)
1 (set) – Clock S output to PWSCAL register (Test only).
0 (clear) – Normal operation.
When TPWSL is one, clock S from the PWM timer is output to PWSCAL register. Normal writing
8
to the PWSCAL register still functions.
DISCP — Disable compare scaled E clock (Test mode only)
1 (set) – Match of period does not reset associated count register (Test only).
0 (clear) – Normal operation.
Bits [5:4] — Not implemented; always read zero
PWEN[4:1] — Pulse width channels 4–1
1 (set) – Channel enabled on the associated port pin.
0 (clear) – Channel disabled.
MOTOROLA
8-32
TIMING SYSTEM
TPG
MC68HC11PH8