MC68HC11PH8 Datasheet, PDF (60/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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08/Apr/97@13:55 [DS97 v 4.1]
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NOSEC — EEPROM security disabled (refer to Section 3.4.4)
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1 (set) – Disable security.
0 (clear) – Enable security.
PH8.DS03/Modes+mem
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NOCOP — COP system disable (refer to Section 10)
1 (set) – COP system disabled.
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0 (clear) – COP system enabled (forces reset on timeout).
ROMON — ROM enable
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1 (set) – ROM/EPROM included in the memory map.
0 (clear) – ROM/EPROM excluded from the memory map.
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In single chip mode, reset sets this bit. In special test mode, reset clears ROMON. On the
MC68HC711PH8, and on the MC68HC11PH8 if selected by a mask option, ROMON can be
modified in expanded and special test modes. In this case, care must be taken to include reset
and interrupt vectors in both internal and external memory maps. The routines for altering
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ROMON should not be located at addresses in the internal ROM/EPROM memory range, but
rather at different external ROM/EPROM addresses or in internal EEPROM.
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EEON — EEPROM enable
1 (set) – EEPROM included in the memory map.
0 (clear) – EEPROM is excluded from the memory map.
3.3.2.2 INIT — RAM and I/O mapping register
RAM & I/O mapping (INIT)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
The internal registers used to control the operation of the MCU can be relocated on 4K boundaries
within the memory space with the use of INIT. This 8-bit special-purpose register can change the
default locations of the RAM and control registers within the MCU memory map. It can be written
to only once within the first 64 E clock cycles after a reset. It then becomes a read-only register.
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RAM[3:0] — RAM map position
These four bits, which specify the upper hexadecimal digit of the RAM address, control the
position of the RAM in the memory map. The RAM can be positioned at the beginning of any 4K
page in the memory map. Refer to Table 3-5.
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MOTOROLA
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OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MC68HC11PH8