MC68HC11PH8 Datasheet, PDF (155/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.5.2 TFLG2 — Timer interrupt flag register 2
Timer interrupt ßag 2 (TFLG2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0025 TOF RTIF PAOVF PAIF 0
0
0
0 0000 0000
Bits of this register indicate the occurrence of timer system events. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled
or interrupt driven system. Clear flags by writing a one to the corresponding bit position(s).
Note:
Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in TMSK2 enable the
corresponding interrupt sources.
TOF — Timer overflow interrupt flag (refer to Section 8.1.4.10)
1 (set) – TCNT has overflowed from $FFFF to $0000.
0 (clear) – No timer overflow has occurred.
RTIF — Real-time interrupt flag
1 (set) – RTI period has elapsed.
0 (clear) – RTI flag has been cleared.
8
The RTIF status bit is automatically set to one at the end of every RTI period.
PAOVF — Pulse accumulator overflow interrupt flag (refer to Section 8.1.8)
PAIF — Pulse accumulator input edge interrupt flag (refer to Section 8.1.8)
Bits [3:0] — Not implemented; always read zero
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-21