MC68HC11PH8 Datasheet, PDF (149/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.4.7 TMSK1 — Timer interrupt mask register 1
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt mask 1 (TMSK1) $0022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I 0000 0000
Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.
Note:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the
corresponding interrupt sources.
OC1I–OC4I — Output compare x interrupt enable
1 (set) – OCx interrupt is enabled.
0 (clear) – OCx interrupt is disabled.
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
I4/O5I — Input capture 4/output compare 5 interrupt enable
1 (set) – IC4/OC5 interrupt is enabled.
0 (clear) – IC4/OC5 interrupt is disabled.
When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt enable bit.
8
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input capture x interrupt enable
1 (set) – ICx interrupt is enabled.
0 (clear) – ICx interrupt is disabled.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-15