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MC68HC11PH8 Datasheet, PDF (159/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit | |||
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8.1.8.1 PACTL â Pulse accumulator control register
Address bit 7
Pulse accumulator control (PACTL) $0026 0
bit 6 bit 5 bit 4 bit 3
PAEN PAMOD PEDGE 0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Four of this registerâs bits control an 8-bit pulse accumulator system. Another bit enables either the
OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system.
Bits [7, 3] â Not implemented; always read zero
PAEN â Pulse accumulator system enable
1 (set) â Pulse accumulator enabled.
0 (clear) â Pulse accumulator disabled.
PAMOD â Pulse accumulator mode
1 (set) â Gated time accumulation mode.
0 (clear) â Event counter mode.
PEDGE â Pulse accumulator edge control
This bit has different meanings depending on the state of the PAMOD bit, as shown:
8
PAMOD PEDGE
Action of clock
0
0 PAI falling edge increments the counter.
0
1 PAI rising edge increments the counter.
1
0 A zero on PAI inhibits counting.
1
1 A one on PAI inhibits counting.
I4/O5 â Input capture 4/output compare 5
1 (set) â Input capture 4 function is enabled (no OC5).
0 (clear) â Output compare 5 function is enabled (no IC4)
RTR[1:0] â RTI interrupt rate selects (refer to Section 8.1.5)
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-25
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