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MC68HC11PH8 Datasheet, PDF (185/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
10
RESETS AND INTERRUPTS
Resets and interrupt operations load the program counter with a vector that points to a new
location from which instructions are to be fetched. A reset immediately stops execution of the
current instruction and forces the program counter to a known starting address. Internal registers
and control bits are initialized so that the MCU can resume executing instructions. An interrupt
temporarily suspends normal program execution whilst an interrupt service routine is being
executed. After an interrupt has been serviced, the main program resumes as if there had been
no interruption.
10.1
Resets
There are four possible sources of reset. Power-on reset (POR) and external reset share the
normal reset vector. The computer operating properly (COP) reset and the clock monitor reset
each has its own vector.
10.1.1 Power-on reset
A positive transition on VDD generates a power-on reset (POR), which is used only for power-up
conditions. POR cannot be used to detect drops in power supply voltages. A delay is imposed
which allows the clock generator to stabilize after the oscillator becomes active. If RESET is at
logical zero at the end of the delay time, the CPU remains in the reset condition until RESET goes
to logical one. A mask option selects one of two delay times; either 128 or 4064 tCYC (internal clock
cycles).
10
Note:
This mask option is not available on the MC68HC711PH8, where the delay time is
4064 tCYC.
It is important to protect the MCU during power transitions. Most M68HC11 systems need an
external circuit that holds the RESET pin low whenever VDD is below the minimum operating level.
This external voltage level detector, or other external reset circuits, are the usual source of reset
in a system. The POR circuit only initializes internal circuitry during cold starts. Refer to Figure 2-3.
MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-1