MC68HC11PH8 Datasheet, PDF (10/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Paragraph
Number
Title
3
OPERATING MODES AND ON-CHIP MEMORY
Page
Number
3.1 Operating modes ...................................................................................................3-1
3.1.1 Single chip operating mode .............................................................................3-1
3.1.2 Expanded operating mode...............................................................................3-1
3.1.3 Special test -mode ...........................................................................................3-2
3.1.4 Special bootstrap mode ...................................................................................3-2
3.2 On-chip memory....................................................................................................3-3
3.2.1 Mapping allocations .........................................................................................3-4
3.2.1.1
RAM ...........................................................................................................3-4
3.2.1.2
ROM and EPROM......................................................................................3-5
3.2.1.3
Bootloader ROM ........................................................................................3-5
3.2.2 Registers..........................................................................................................3-5
3.3 System initialization ...............................................................................................3-10
3.3.1 Mode selection.................................................................................................3-10
3.3.1.1
HPRIO — Highest priority I-bit interrupt & misc. register ...........................3-11
3.3.2 Initialization ......................................................................................................3-12
3.3.2.1
CONFIG — System configuration register .................................................3-12
3.3.2.2
INIT — RAM and I/O mapping register ......................................................3-14
3.3.2.3
INIT2 — EEPROM mapping and MI BUS delay register............................3-16
3.3.2.4
OPTION — System configuration options register 1..................................3-17
3.3.2.5
OPT2 — System configuration options register 2 ......................................3-18
3.3.2.6
BPROT — Block protect register................................................................3-21
3.3.2.7
TMSK2 — Timer interrupt mask register 2.................................................3-22
3.4 EPROM, EEPROM and CONFIG register .............................................................3-23
3.4.1 EPROM............................................................................................................3-23
3.4.1.1
EPROG — EPROM programming control register.....................................3-23
3.4.1.2
EPROM programming ................................................................................3-24
3.4.2 EEPROM .........................................................................................................3-25
3.4.2.1
PPROG — EEPROM programming control register ..................................3-25
3.4.2.2
EEPROM bulk erase ..................................................................................3-27
3.4.2.3
EEPROM row erase ...................................................................................3-28
3.4.2.4
EEPROM byte erase ..................................................................................3-28
3.4.3 CONFIG register programming........................................................................3-29
3.4.4 RAM and EEPROM security............................................................................3-30
4
PARALLEL INPUT/OUTPUT
4.1 Port A.....................................................................................................................4-2
4.1.1 PORTA — Port A data register ........................................................................4-2
4.1.2 DDRA — Data direction register for port A .....................................................4-2
MOTOROLA
ii
TABLE OF CONTENTS
TPG
MC68HC11PH8