MC68HC11PH8 Datasheet, PDF (67/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

PH8.DS03/Modes+mem
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[DS97 v 4.1] 08/Apr/97@13:55
3.3.2.6 BPROT — Block protect register
Block protect (BPROT)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0035 BULKP 0 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
BPROT prevents accidental writes to EEPROM and the CONFIG register. The bits in this register
can be written to zero only once during the first 64 E clock cycles after reset in the normal modes;
they can be set at any time. Once the bits are cleared, the EEPROM array and the CONFIG
register can be programmed or erased. Setting the bits in the BPROT register to logic one protects
the EEPROM and CONFIG register until the next reset. Refer to Table 3-7.
BULKP — Bulk erase of EEPROM protect
1 (set) – EEPROM cannot be bulk or row erased.
0 (clear) – EEPROM can be bulk erased normally.
Bit 6 — Not implemented; always reads zero.
BPRT4 — Block protect bit for top 256 bytes of EEPROM (see below)
PTCON — Protect for CONFIG register
1 (set) – CONFIG register cannot be programmed or erased.
0 (clear) – CONFIG register can be programmed or erased normally.
Note that, in special modes, CONFIG may be written regardless of the state of PTCON.
BPRT[4:0] — Block protect bits for EEPROM
1 (set) – Protection is enabled for associated block; it cannot be programmed
or erased.
0 (clear) – Protection disabled for associated block.
Each of these five bits protects a block of EEPROM against writing or erasure, as follows:
1
2
3
4
5
6
7
8
9
10
11
Table 3-7 EEPROM block protect
Bit name Block protected Block size
BPRT0 $xD00Ð$xD1F 32 bytes
BPRT1 $xD20Ð$xD5F 64 bytes
BPRT2 $xD60Ð$xDDF 128 bytes
BPRT3 $xDE0Ð$xEFF 288 bytes
BPRT4 $xF00Ð$xFFF 256 bytes
12
13
14
MC68HC11PH8
OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MOTOROLA
3-21
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