MC68HC11PH8 Datasheet, PDF (191/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

PAREN — Pull-up assignment register enable (refer to Section 4)
1 (set) – PPAR register enabled; pull-ups can be enabled using PPAR.
0 (clear) – PPAR register disabled; all pull-ups disabled.
NOSEC — EEPROM security disabled (refer to Section 3)
1 (set) – Disable security.
0 (clear) – Enable security.
NOCOP — COP system disable
1 (set) – COP system disabled.
0 (clear) – COP system enabled (forces reset on timeout).
ROMON — ROM/EPROM enable (refer to Section 3)
1 (set) – ROM/EPROM included in the memory map.
0 (clear) – ROM/EPROM excluded from the memory map.
EEON — EEPROM enable (refer to Section 3)
1 (set) – EEPROM included in the memory map.
0 (clear) – EEPROM excluded from the memory map.
10.2
Effects of reset
When a reset condition is recognized, the internal registers and control bits are forced to an initial
state. Depending on the cause of the reset and the operating mode, the reset vector can be
fetched from any of six possible locations, as shown in Table 10-3.
10
Table 10-3 Reset cause, reset vector and operating mode
Cause of reset Normal mode vector Special test or bootstrap
POR or RESET pin
$FFFE, $FFFF
$BFFE, $BFFF
Clock monitor failure
$FFFC, $FFFD
$BFFC, $BFFD
COP watchdog timeout $FFFA, $FFFB
$BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them to known start-up states,
as described in the following paragraphs.
MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-7