MC68HC11PH8 Datasheet, PDF (54/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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08/Apr/97@13:55 [DS97 v 4.1]
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PH8.DS03/Modes+mem
Table 3-2 Register and control bit assignments (Sheet 3 of 4)
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
reserved
$0046
reserved
$0047
reserved
$0048
reserved
$0049
reserved
$004A
reserved
$004B
SPI2 control (SP2CR)
$004C SP2IE SP2E GWOM MSTR2 CPOL2 CPHA2 SP2R1 SP2R0 0000 01uu
SPI2 status (SP2SR)
$004D SP2IF WCOL2 0 MODF2 0
0
0
0 0000 0000
SPI2 data (SP2DR)
$004E (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
SPI2 control options (SP2OPT) $004F 0
0
0
0 LSBF2 SP2R2 0
0 0000 0000
SCI2/MI baud high (S2BDH)
$0050 B2TST B2SPL B2RST S2B12 S2B11 S2B10 S2B9 S2B8 0000 0000
SCI2/MI baud low (S2BDL)
$0051 S2B7 S2B6 S2B5 S2B4 S2B3 S2B2 S2B1 S2B0 0000 0100
SCI2/MI control 1 (S2CR1)
$0052 LOPS2 WOMS2 MIE2 M2 WAKE2 ILT2 PE2 PT2 0000 0000
SCI2/MI control 2 (S2CR2)
$0053 TIE2 TCIE2 RIE2 ILIE2 TE2 RE2 RWU2 SBK2 0000 0000
SCI2/MI status 1 (S2SR1)
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2 NF2 FE2 PF2 1100 0000
SCI2/MI status 2 (S2SR2)
$0055 0
0
0
0
0
0
0 RAF2 0000 0000
SCI2/MI data high (S2DRH)
$0056 R8B T8B 0
0
0
0
0
0 undeÞned
SCI2/MI data low (S2DRL)
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undeÞned
reserved
$0058
8-bit modulus timer A data (T8ADR) $0059 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
8-bit modulus timer B data (T8BDR) $005A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
8-bit modulus timer C data (T8CDR) $005B (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
reserved
$005C
8-bit modulus timer A control (T8ACR) $005D T8AI T8AF 0
0
0 CSA2 CSA1 CSA0 0000 0000
8-bit modulus timer B control (T8BCR) $005E T8BI T8BF 0
0 PRB CSB2 CSB1 CSB0 0000 0000
8-bit modulus timer C control (T8CCR) $005F T8CI T8CF 0
0 PRC CSC2 CSC1 CSC0 0000 0000
Pulse width clock select (PWCLK) $0060 CON34 CON12 PCKA2 PCKA1 0 PCKB3 PCKB2 PCKB1 0000 0000
Pulse width polarity select (PWPOL) $0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
Pulse width scale (PWSCAL) $0062 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Pulse width enable (PWEN)
$0063 TPWSL DISCP 0
0 PWEN4 PWEN3 PWEN2 PWEN1 0000 0000
Pulse width count 1 (PWCNT1) $0064 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Pulse width count 2 (PWCNT2) $0065 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Pulse width count 3 (PWCNT3) $0066 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Pulse width count 4 (PWCNT4) $0067 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
Pulse width period 1 (PWPER1) $0068 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
MOTOROLA
3-8
OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MC68HC11PH8