MC68HC11PH8 Datasheet, PDF (104/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

5.6.5 SCSR2 — SCI status register 2
SCI1 status 2 (SCSR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0075 0
0
0
0
0
0
0 RAF 0000 0000
In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero.
Bits [7:1] — Not implemented; always read zero
RAF — Receiver active flag (read only)
5
1 (set) – A character is being received.
0 (clear) – A character is not being received.
5.6.6 SCDRH, SCDRL — SCI data high/low registers
SCI1 data high (SCDRH)
SCI1 data low (SCDRL)
Address bit 7
$0076 R8
$0077 R7T7
bit 6
T8
R6T6
bit 5
0
R5T5
bit 4
0
R4T4
bit 3
0
R3T3
bit 2
0
R2T2
bit 1
0
R1T1
bit 0
0
R0T0
State
on reset
undeÞned
undeÞned
SCDRH/SCDRL is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the receive data
buffer and writes access the transmit data buffer. Data received or transmitted is double buffered.
If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if 9-bit
data format is used, the upper register should be written first to ensure that it is transferred to the
transmitter shift register with the lower register.
R8 — Receiver bit 8
Ninth serial data bit received when SCI is configured for a nine data bit operation
T8 — Transmitter bit 8
Ninth serial data bit transmitted when SCI is configured for a nine data bit operation
Bits [5:0] — Not implemented; always read zero
R/T[7:0] — Receiver/transmitter data bits [7:0]
SCI data is double buffered in both directions.
MOTOROLA
5-12
SERIAL COMMUNICATIONS INTERFACE
TPG
MC68HC11PH8