MC68HC11PH8 Datasheet, PDF (68/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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08/Apr/97@13:55 [DS97 v 4.1]
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PH8.DS03/Modes+mem
3.3.2.7 TMSK2 — Timer interrupt mask register 2
2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
3
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
PR[1:0] are time-protected control bits and can be changed only once and then only within the first
64 bus cycles after reset in normal modes.
4
Note: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the
corresponding interrupt sources.
5
TOI — Timer overflow interrupt enable (Refer to Section 8)
1 (set) – Interrupt requested when TOF is set.
6
0 (clear) – TOF interrupts disabled.
7
8
9
10
11
12
13
14
15
RTII — Real-time interrupt enable (Refer to Section 8)
1 (set) – Interrupt requested when RTIF set.
0 (clear) – RTIF interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (Refer to Section 8)
1 (set) – Interrupt requested when PAOVF set.
0 (clear) – PAOVF interrupts disabled.
PAII — Pulse accumulator interrupt enable (Refer to Section 8)
1 (set) – Interrupt requested when PAIF set.
0 (clear) – PAIF interrupts disabled.
Bits [3, 2] — Not implemented; always read zero.
PR[1:0] — Timer prescaler select
These two bits select the prescale rate for the main 16-bit free-running timer system. These bits
can be written only once during the first 64 E clock cycles after reset in normal modes, or at any
time in special modes. Refer to the following table:
MOTOROLA
3-22
PR[1:0] Prescale factor
00
1
01
4
10
8
11
16
OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MC68HC11PH8