MC68HC11PH8 Datasheet, PDF (81/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

4.2
Port B
Port B is an 8-bit bidirectional port, with both data and data direction registers. In addition to their
I/O capability, port B pins are used as the non-multiplexed high order address pins, as shown in
the following table.
Pin
Alternate
function
PB0
A8

4
PB1
A9


In expanded or test
PB2
A10
PB3
A11
PB4
A12/LCD4



mode, the pins
become the high



order address lines
and port B is not
PB5
A13/LCD5
PB6
A14/ LCD6



included in the
memory map.

PB7
A15/LCD7

The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port B pins
are high-impedance inputs with selectable internal pull-up resistors (see Section 4.9). In
expanded or test mode, port B pins are high order address outputs and PORTB/DDRB are not in
the memory map. Alternatively, four LCD segment drivers can be enabled, in all modes, on
PB4–PB7 (See Section 2.12).
4.2.1 PORTB — Port B data register
Port B data (PORTB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 undeÞned
The bits may be read and written at any time and are not affected by reset.
4.2.2 DDRB — Data direction register for port B
Data direction B (DDRB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0002 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000
DDB[7:0] — Data direction for port B
1 (set) – The corresponding pin is configured as an output.
0 (clear) – The corresponding pin is configured as an input.
MC68HC11PH8
PARALLEL INPUT/OUTPUT
TPG
MOTOROLA
4-3