MC68HC11PH8 Datasheet, PDF (29/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.2
RESET
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known
2
start-up state. It also acts as an open-drain output to indicate that an internal failure has been
detected in either the clock monitor or the COP watchdog circuit. The CPU distinguishes between
internal and external reset conditions by sensing whether the reset pin rises to a logic one in less
than four E clock cycles after an internal reset has been released. It is therefore not advisable to
connect an external resistor-capacitor (RC) power-up delay circuit to the reset pin of M68HC11
devices because the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred. Refer to Section 10 for further information.
Figure 2-3 illustrates a typical reset circuit that includes an external switch together with a low
voltage inhibit circuit, to prevent power transitions, or RAM or EEPROM corruption.
V_DD
V_DD
2
IN
4.7 kΩ
1
RESET
MC34064
GND
V_DD
3
To M68HC11
RESET
Manual
reset
4.7 kΩ
4.7 kΩ
2
1 µF
IN
RESET ¹
MC34164
GND
3
Figure 2-3 External reset circuitry
2.3
Crystal driver and external clock input (XTAL, EXTAL)
These two pins provide the interface for either a crystal or a CMOS compatible clock to control the
internal clock generator circuitry. If the PLL circuit is not being used to provide the E clock, the
frequency applied to these pins must be four times higher than the desired E clock rate. Figure 2-4
shows oscillator connections that should be used when the PLL is disabled, and Figure 2-5 shows the
connections that should be used when the PLL is enabled.
MC68HC11PH8
PIN DESCRIPTIONS
TPG
MOTOROLA
2-3