MC68HC11PH8 Datasheet, PDF (34/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.5.2 Synchronization of PLL with subsystems
2
If the MCS bit in PLLCR is set, then the SCI and timer clocks run off the PLL output (4XCLK) as
does the CPU. If MCS is cleared, then the timer and SCI subsystems operate off the EXTALi
frequency, but are accessed by the CPU relative to the internal PH2 signal. In this case, although
EXTALi is used as the reference for the PLL, the PH2 clock and the module clocks for the timer
and the SCI are not synchronized. In order to ensure synchronized data, special circuitry has been
incorporated into both subsystems.
2.5.3 Changing the PLL frequency
The PLL output frequency can be changed by altering the contents of the SYNR register (see
Section 2.5.4.2). To prevent possible bursts of high frequency operation during the reconfiguration
of the PLL, the following sequence should be performed:
1) Switch to the low frequency bus rate (BCS = 0).
2) Disable the PLL (PLLON = 0).
3) Change the value in SYNR.
4) Enable the PLL (PLLON = 1).
5) Wait a time t_PLLS for the PLL frequency to stabilize.
6) Switch to the high frequency bus rate (BCS = 1).
2.5.4 PLL registers
Two registers are used to control the operation of the MC68HC11PH8 phase locked loop circuitry.
These are the PLL control register and the synthesizer program register, each of which is
described below.
MOTOROLA
2-8
PIN DESCRIPTIONS
TPG
MC68HC11PH8