MC68HC11PH8 Datasheet, PDF (119/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

6.6.2 S2BDH, S2BDL — MI BUS clock rate control registers
SCI2/MI baud high (S2BDH)
SCI2/MI baud low (S2BDL)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
$0050 B2TST B2SPL B2RST S2B12 S2B11 S2B10 S2B9
$0051 S2B7 S2B6 S2B5 S2B4 S2B3 S2B2 S2B1
bit 0
State
on reset
S2B8 0000 0000
S2B0 0000 0100
The contents of this register determine the clock rate for MI BUS.
S2B[12:0] — SCI baud rate/ MI BUS clock rate selects
Use the following formula to calculate MI BUS clock rate. Refer to the table of baud rate control
values (see Table 5-1) for example rates:
MI BUS clock rate = ₁---S₆----T-_×---⁴--₍-X-₂----BC----RK-----₎
6
where the baud rate control value (BR) is the contents of S2BDH/L (BR = 1, 2, 3,... 8191).
The clock rate generator is disabled if BR = 0, or if neither the receiver nor transmitter is enabled
(both RE and TE in SCCR2 are cleared).
Writes to the baud rate registers will only be successful if the last (or only) byte written is SCBDL.
The use of an STD instruction is recommended as it guarantees that the bytes are written in the
correct order.
Note:
ST4XCK may be the output of the PLL circuit or it may be the EXTAL input of the MCU.
Selection is made by the MCS bit in the PLLCR (see Section 2.5).
6.6.3 S2CR1 — MI BUS control register 1
SCI2/MI control 1 (S2CR1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0052 Ñ WOMS2 MIE2 Ñ Ñ Ñ Ñ PT2 0000 0000
WOMS2 — Wired-OR mode for MI BUS pins (PG0, PG1)
1 (set) – TXD2 and RXD2 are open drains if operating as outputs.
0 (clear) – TXD2 and RXD2 operate normally.
MIE2 — Motorola interface bus enable 2
1 (set) – MI BUS is enabled for this subsystem.
0 (clear) – The SCI functions normally.
When MIE2 is set, the SCI2 registers, bits and pins assume the functionality required for MI BUS.
MC68HC11PH8
MOTOROLA INTERCONNECT BUS (MI BUS)
TPG
MOTOROLA
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