MC68HC11PH8 Datasheet, PDF (187/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table 10-1 COP timer rate select (PLL disabled)
CR[1:0]
Divide
E/2¹⁵ by
EXTALi = 8MHz:
timeout⁽¹⁾
EXTALi = 12MHz:
timeout⁽¹⁾
EXTALi = 16MHz:
timeout⁽¹⁾
00
1
16.384 ms
10.923 ms
8.192 ms
01
4
65.536 ms
43.691 ms
32.768 ms
10
16
262.14 ms
174.76 ms
131.07 ms
11
64
1.049 sec
699.05 ms
524.29 ms
E=
2.0 MHz
3.0 MHz
4.0 MHz
(1) The timeout period has a tolerance of Ð0/+one cycle of the E/2¹⁵ clock due to
the asynchronous implementation of the COP circuitry. For example, with
EXTALi = 8MHz, the uncertainty is Ð0/+16.384ms. See also the M68HC11
Reference Manual, (M68HC11RM/AD).
Table 10-2 COP timer rate select (PLL enabled)
CR[1:0]
Divide
CLK64 by
CLK64 = 4.096 kHz:
timeout⁽¹⁾
00
4
1 ms
01
16
3.9 ms
10
64
15.6 ms
11
256
62.5 sec
CLK64 =64 Hz:
timeout⁽¹⁾
62.5 ms
250 ms
1s
4s
CLK64 = 4 Hz:
timeout⁽¹⁾
1s
4s
16 s
64 s
(1) The timeout period has a tolerance of Ð0/+one cycle of the CLK64/4 clock due to
the asynchronous implementation of the COP circuitry. For example, with
CLK64 = 64 Hz, the uncertainty is Ð0/+62.5ms. See also the M68HC11
Reference Manual, (M68HC11RM/AD).
10.1.3.1 COPRST — Arm/reset COP timer circuitry register
10
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
COP timer arm/reset (COPRST) $003A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) not affected
Complete the following reset sequence to service the COP timer. Write $55 to COPRST to arm
the COP timer clearing mechanism. Then write $AA to COPRST to clear the COP timer. Executing
instructions between these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.
MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-3