MC68HC11PH8 Datasheet, PDF (131/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.5.4 OPT2 — System configuration options register 2
System conÞg. options 2 (OPT2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0038 LIRDV CWOM STRCH IRVNE LSBF SPR2 EXT4X DISE x00x 0000
LIRDV — LIR driven (refer to Section 3)
1 (set) – Enable LIR push-pull drive.
0 (clear) – LIR not driven on MODA/LIR pin.
CWOM — Port C wired-OR mode (refer to Section 4)
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
STRCH — Stretch external accesses (refer to Section 3)
1 (set) – Off-chip accesses are extended by one E clock cycle.
0 (clear) – Normal operation.
7
IRVNE — Internal read visibility/not E (refer to Section 3)
1 (set) – Data from internal reads is driven out of the external data bus.
0 (clear) – No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set) – E pin is driven low.
0 (clear) – E clock is driven out from the chip.
LSBF — LSB first enable
1 (set) – SPI1 data is transferred LSB first.
0 (clear) – SPI1 data is transferred MSB first.
If this bit is set, data, which is usually transferred MSB first, is transferred LSB first. LSBF does not
affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 — SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the
SPCR, this bit specifies the SPI clock rate. Refer to Table 7-1.
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-9