MC68HC11PH8 Datasheet, PDF (201/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.4.5 Maskable interrupts
The maskable interrupt structure of the MCU can be extended to include additional external
interrupt sources through the IRQ pin. The default configuration of this pin is a low-level sensitive
wired-OR network. When an event triggers an interrupt, a software accessible interrupt flag is set.
When enabled, this flag causes a constant request for interrupt service. After the flag is cleared,
the service request is released.
10.4.6 Reset and interrupt processing
The following flow diagrams illustrate the reset and interrupt process. Figure 10-1 and Figure 10-2
illustrate how the CPU begins from a reset and how interrupt detection relates to normal opcode
fetches. Figure 10-3 to Figure 10-4 provide an expanded version of a block in Figure 10-1 and illustrate
interrupt priorities. Figure 10-7 shows the resolution of interrupt sources within the SCI subsystem.
10.5
Low power operation
Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition
suspends processing and reduces power consumption to an intermediate level. The STOP
condition turns off all on-chip clocks and reduces power consumption to an absolute minimum
while retaining the contents of all bytes of the RAM.
10.5.1 WAIT
The WAI opcode places the MCU in the WAIT condition, during which the CPU registers are stacked
and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an
external IRQ, an XIRQ, or any of the internally generated interrupts, such as the timer or serial
interrupts. The on-chip crystal oscillator remains active throughout the WAIT stand-by period.
The reduction of power in the WAIT condition depends on how many internal clock signals driving
on-chip peripheral functions can be shut down. The CPU is always shut down during WAIT. While
in the wait state, the address/data bus repeatedly runs read cycles to the address where the CCR
contents were stacked. The MCU leaves the wait state when it senses any interrupt that has not
been masked.
The PH2 clock to the free-running timer system is stopped if the I-bit is set and the COP system
is disabled by NOCOP being set. In addition, further power can be saved if the clock to the 16-bit
counter is stopped by clearing the T16EN bit in PLLCR, with the PLL active (see Section 8.1.1.1).
Several other systems can also be in a reduced power consumption state depending on the state
of software-controlled configuration control bits. Power consumption by the analog-to-digital (A/D)
converter is not affected significantly by the WAIT condition. However, the A/D converter current
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MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-17