MC68HC11PH8 Datasheet, PDF (254/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

CD–CA - bits in ADCTL 9-9
CFORC — Timer compare force reg. 8-12
charge pump, A/D 9-3
CLK4X - bit in CONFIG 3-13
, clock monitor 10-4 10-5
, clock rate, MI BUS 6-7 6-9
clocks
, 4XCLK 2-9 2-10
A/D 9-4
CMOS compatible 2-3
, E 2-3 3-19
, monitor reset 10-4 10-5
PWM 8-30
SPI 7-4
ST4XCK 6-7
stretching 3-19
, timer divider chains 8-5 8-6
CME - bit in OPTION 10-5
coherency, timer 8-12
CON12 - bit in PWCLK 8-28
CON34 - bit in PWCLK 8-28
concatenation, of PWM 8-28
CONFIG — System configuration reg. 3-12
programming 3-29
configuration 3-12
, , , conversion, A/D 9-3 9-4 9-4 9-5
, COP 8-2 8-23
CONFIG — Configuration control reg. 10-6
COPRST — Arm/reset COP timer circuitry reg. 10-3
enable 10-7
OPTION — System configuration options reg. 1 10-4
, rates 10-3 10-5
, , reset 10-2 10-3 10-9
timeout 10-2
COPRST — Arm/reset COP timer circuitry reg. 10-3
corruption
of A/D 4-6
of memory 2-3
, , CPHA - bit in SPCR 7-3 7-4 7-7
CPOL - bit in SPCR 7-6
CPU 11-1
accumulators (A, B and D) 11-2
architecture 11-1
CCR — condition code reg. 11-4
index registers (IX, IY) 11-2
program counter (PC) 11-4
programming model 11-1
registers 11-1
reset 10-8
CR[1:0] - bits in OPTION 10-5
CSA[2:0] - bits in T8ACR 8-38
CSB[2:0] - bits in T8BCR 8-39
CSC[2:0] - bits in T8CCR 8-40
CSEL - bit in OPTION 9-6
CWOM - bit in OPT2 4-12
D
DAC 9-3
data format, SCI 5-2
data types 11-6
DDA[7:0] - bits in DDRA 4-2
DDB[7:0] - bits in DDRB 4-3
DDC[7:0] - bits in DDRC 4-4
DDD[5:0] - bits in DDRD 4-5
DDF[7:0] - bits in DDRF 4-7
DDG[7:0] - bits in DDRG 4-8
DDH[7:0] - bits in DDRH 4-9
DDRA — Data direction reg. for port A 4-2
DDRB — Data direction reg. for port B 4-3
DDRC — Data direction reg. for port C 4-4
DDRD — Data direction reg. for port D 4-5
DDRF — Data direction reg. for port F 4-7
DDRG — Data direction reg. for port G 4-8
DDRH — Data direction reg. for port H 4-9
development tools C-1
DIR - direct addressing mode 11-7
DISCP - bit in PWEN 8-32
DISE - bit in OPT2 3-20
DLY - bit in OPTION 3-17
mask option 3-17
duty cycle, PWM 8-34
DWOM - bit in SPCR 7-6
E
E clock pin 2-5
EDGxA and EDGxB - bits in TCTL2 8-9
EELAT - bit in PPROG 3-26
EEON - bit in CONFIG 3-14
EEPGM - bit in PPROG 3-26
– EEPROM 3-25 3-28
erased state ($FF) 3-25
– erasing 3-27 3-28
PPROG — EEPROM programming control reg. 3-25
security 3-30
EEx - bits in INIT2 3-16
eight bit modulus timers - see 8-bit modulus timers
ELAT - bit in EPROG 3-23
EPGM - bit in EPROG 3-24
EPROG — EPROM programming control reg. 3-23
, – EPROM 3-5 3-23 3-25
device 1-1
EPROG — EPROM programming control reg. 3-23
erased state ($FF) 3-23
programming 3-24
ERASE - bit in PPROG 3-26
erased state
EEPROM ($FF) 3-25
EPROM ($FF) 3-23
error detection, SCI 5-5
ESD protection A-1
EVEN - bit in PPROG 3-25
event counter - see pulse accumulator
MOTOROLA
vi
INDEX
TPG
MC68HC11PH8