MC68HC11PH8 Datasheet, PDF (183/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

MULT — Multiple-channel/single-channel control
1 (set) – Each A/D channel has a result register allocated to it.
0 (clear) – Four consecutive conversions from the same A/D channel are stored
in the results registers.
When this bit is clear, the A/D converter system is configured to perform four consecutive
conversions on the single channel specified by the four channel select bits CD–CA (bits 3–0 of the
ADCTL register). When this bit is set, the A/D system is configured to perform a conversion on
each of the four channels where each result register corresponds to one channel.
Note:
When the multiple-channel continuous scan mode is used, extra care is needed in the
design of circuitry driving the A/D inputs. The charge on the capacitive DAC array before
the sample time is related to the voltage on the previously converted channel. A charge
share situation exists between the internal DAC capacitance and the external circuit
capacitance. Although the amount of charge involved is small, the rate at which it is
repeated is every 64 µs for an E clock of 2 MHz. The RC charging rate of the external circuit
must be balanced against this charge sharing effect to avoid errors in accuracy. Refer to the
M68HC11 Reference Manual (M68HC11RM/AD) for further information.
CD–CA — Channel selects D–A
When a multiple channel mode is selected (MULT = 1), the two least significant channel select bits
(CB and CA) have no meaning and the CD and CC bits specify which group of four channels is to
be converted.
9
Channel select
control bits ^{Channel Result in ADRx}
signal if MULT = 1
CD:CC:CB:CA
0000
AD0
ADR1
0001
AD1
ADR2
0010
AD2
ADR3
0011
AD3
ADR4
0100
AD4
ADR1
0101
AD5
ADR2
0110
AD6
ADR3
0111
AD7
ADR4
10XX
1100
1101
1110
1111
reserved
V_RH(1)
V_RL(1)
V_RH/2⁽¹⁾
reserved⁽¹
)
Ñ
ADR1
ADR2
ADR3
ADR4
MC68HC11PH8
ANALOG-TO-DIGITAL CONVERTER
TPG
MOTOROLA
9-9