MC68HC11PH8 Datasheet, PDF (211/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

11
CPU CORE AND INSTRUCTION SET
This section discusses the M68HC11 central processing unit (CPU) architecture, its addressing
modes and the instruction set. For more detailed information on the instruction set, refer to the
M68HC11 Reference Manual (M68HC11RM/AD).
The CPU is designed to treat all peripheral, I/O and memory locations identically, as addresses in
the 64Kbyte memory map. This is referred to as memory-mapped I/O. There are no special
instructions for I/O that are separate from those used for memory. This architecture also allows
accessing an operand from an external memory location with no execution-time penalty.
11.1
Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were
memory locations. The seven registers are shown in Figure 11-1 and are discussed in the
following paragraphs.
7 Accumulator A 0 7 Accumulator B 0
15
Double accumulator D
0
15
Index register X
0
15
Index register Y
0
15
Stack pointer
0
15
Program counter
0
Condition code register
SXH I NZVC
A:B
D
IX
IY
SP
PC
CCR
Carry
Overßow
Zero
Negative
I Interrupt mask
Half carry (from bit 3)
X Interrupt mask
Stop disable
Figure 11-1 Programming model
11
MC68HC11PH8
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
11-1