MC68HC11PH8 Datasheet, PDF (124/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.2
SPI transfer formats
During an SPI transfer, data is simultaneously transmitted and received. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave select
line allows individual selection of a slave SPI device; slave devices that are not selected do not
interfere with SPI bus activities. On a master SPI device, the select line can optionally be used to
indicate a multiple master bus contention. Refer to Figure 7-2.
MCU
system clock
8-bit shift register
Read data buffer
7
Divider
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128
Shift control logic
Select
SPI clock (master)
Clock
logic
OPT2 Ð Options register 2
SPI control
MSTR
SPE
SPIE
S
MISO
PD2
M
M
MOSI
S
PD3
Pin
control
logic
S
SCK
M
PD4
SS
PD5
SPSR Ð SPI status register
SPI interrupt
request
SPCR Ð SPI control register
Internal bus
SPDR Ð SPI data register
Figure 7-1 SPI block diagram
MOTOROLA
7-2
SERIAL PERIPHERAL INTERFACE
TPG
MC68HC11PH8