MC68HC11PH8 Datasheet, PDF (234/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

A.5.2 PLL control timing
(VDD = 5.0Vdc ±10%, VSS = 0Vdc, T_A = T_L to T_H unless otherwise noted)
Characteristic
Symbol
Mask option 1
Min Typical Maximum
PLL reference frequency
System frequency
PLL output frequency
External clock operation
Capacitor on pin XFC
PLL stabilization time⁽²⁾
4XCLK stability⁽³⁾⁽⁴⁾
Short term
Long term
f_REF
25 32
50
f_SYS
dc Ñ
4
f_VCOOUT 0.05 Ñ
16
f_XTAL
dc
16
C_XFC
Ñ 47
Ñ
t_PLLS
Ñ 20
TBD
C_STAB
TBD Ñ
TBD
TBD Ñ
TBD
Mask option 2⁽¹⁾
Min Typical Maximum
50
614
2000
dc
Ñ
4
0.1
Ñ
16
dc
16
Ñ
47
Ñ
Ñ
10
TBD
Units
kHz
MHz
nF
ms
TBD Ñ
TBD
%
TBD Ñ
TBD
(1) This mask option does not exist on the MC68HC711PH8, on which the PLL is optimized for use at 32kHz.
(2) Assumes that stable VDDSYN is applied, that an external Þlter capacitor with a value of 47nF is attached to the XFC pin,
and that the crystal oscillator is stable. Stabilization time is measured from power-up to RESET release. This speciÞcation
also applies to the period required for PLL stabilization after changing the X and Y frequency control bits in the
synthesizer control register (SYNR) while PLL is running, and to the period required for the clock to stabilize after WAIT
with WEN = 1.
(3) Short term stability is the average deviation from programmed frequency measured over a 2µs interval at maximum f_SYS,
Long term 4XCLK stability is the average deviation from programmed frequency measured over a 1ms interval at
maximum f_SYS. Stability is measured with a stable external clock applied Ñ variation in crystal oscillator frequency is
additive to this Þgure.
(4) This parameter is periodically sampled rather than 100% tested.
12
MOTOROLA
A-10
ELECTRICAL SPECIFICATIONS (STANDARD)
TPG
MC68HC11PH8