MC68HC11PH8 Datasheet, PDF (236/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

A.5.4 Serial peripheral interface timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Num
Characteristic ⁽¹⁾
2.0 MHz
3.0 MHz
4.0 MHz
Symbol
Unit
Min. Max. Min. Max. Min. Max.
Operating frequency
Master f_OP(M)
0
0.5 0 0.5
0 0.5 f_OP
Slave f_OP(S)
0 2.0 0 3.0 0 4.0 MHz
1 Cycle time
2 Enable lead time ⁽²⁾
3 Enable lag time ⁽²⁾
Master t_CYC(M) 2.0 Ñ 2.0 Ñ 2.0 Ñ t_CYC
Slave t_CYC(S) 500 Ñ 333 Ñ 250 Ñ ns
Master t_LEAD(M) Ñ
Slave t_LEAD(S) 250
Ñ
Ñ
Ñ
240
Ñ
Ñ
Ñ
200
Ñ
Ñ
ns
Master t_LAG(M) Ñ
Slave t_LAG(S) 250
Ñ
Ñ
Ñ
240
Ñ
Ñ
Ñ
200
Ñ
Ñ
ns
4 Clock (SCK) high time
Master t_W(SCKH)M 340
Slave t_W(SCKH)S 190
Ñ
Ñ
227
127
Ñ
Ñ
130
85
Ñ
Ñ
ns
5 Clock (SCK) low time
Master t_W(SCKL)M 340
Slave t_W(SCKL)S 190
Ñ
Ñ
227
127
Ñ
Ñ
130
85
Ñ
Ñ
ns
6 Input data set-up time
Master
Slave
t_SU(M)
t_SU(S)
100
100
Ñ
Ñ
100
100
Ñ
Ñ
100
100
Ñ
Ñ
ns
7 Input data hold time
Master t_H(M)
Slave t_H(S)
100 Ñ 100 Ñ 100 Ñ
100 Ñ 100 Ñ 100 Ñ
ns
8 Access time (from high-z to data active) Slave t_A
0 120 0 120 0 120 ns
9 Disable time (hold time to high-z state) Slave t_DIS
10 Data valid (after enable edge) ⁽³⁾
t_V(S)
Ñ 300 Ñ 300 Ñ 300 ns
Ñ 240 Ñ 167 Ñ 125 ns
11 Output data hold time (after enable edge)
12 Rise time ⁽³⁾
t_HO
0 Ñ 0 Ñ 0 Ñ ns
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)
13 Fall time ⁽³⁾
t_RM
Ñ 100 Ñ 100 Ñ 100 ns
t_RS
Ñ 2.0 Ñ 2.0 Ñ 2.0 µs
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)
t_FM
Ñ 100 Ñ 100 Ñ 100 ns
t_FS
Ñ 2.0 Ñ 2.0 Ñ 2.0 µs
(1) All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
(2) Signal production depends on software.
(3) Assumes 200pF load on all SPI pins.
12
MOTOROLA
A-12
ELECTRICAL SPECIFICATIONS (STANDARD)
TPG
MC68HC11PH8