MC68HC11PH8 Datasheet, PDF (258/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

PWCNT1–4 — PWM timer counter reg. 1 to 4 8-33
PWDTY1–4 — PWM timer duty cycle reg. 1 to 4 8-34
PWEN — PWM timer enable reg. 8-32
PWEN[4:1] - bits in PWEN 8-32
PWM 8-27
16-bit operation 8-28
block diagram 8-29
boundary conditions 8-34
clock select 8-30
, duty cycle 8-27 8-34
periods 8-27
pins 8-27
PWCLK — PWM clock prescaler and 16-bit select reg.
8-28
PWCNT1–4 — PWM timer counter reg. 1 to 4 8-33
PWDTY1–4 — PWM timer duty cycle reg. 1 to 4 8-34
PWEN — PWM timer enable reg. 8-32
PWPER1–4 — PWM timer period reg. 1 to 4 8-33
PWPOL — PWM timer polarity & clock source select
reg. 8-31
PWSCAL — PWM timer prescaler reg. 8-31
PWPER1–4 — PWM timer period reg. 1 to 4 8-33
PWPOL — PWM timer polarity & clock source select reg.
8-31
PWSCAL — PWM timer prescaler reg. 8-31
R
, R/T[7:0] - bits in S2DRL 5-17 6-12
R/T[7:0] - bits in SCDRL 5-12
R/W pin 2-13
R8 - bit in SCDRH 5-12
R8B - bit in S2DRH 5-17
RAF - bit in SCSR2 5-12
, RAF2 - bit in S2SR2 5-17 6-12
RAM 3-4
data retention 3-5
security 3-30
RAM[3:0] - bit in INIT 3-14
ratiometric conversions 9-5
RBOOT - bit in HPRIO 3-11
RDRF - bit in SCSR1 5-10
, RDRF2 - bit in S2SR1 5-16 6-11
RE - bit in SCCR2 5-9
, RE2 - bit in S2CR2 5-16 6-10
real-time interrupt - see RTI
receiver flags, SCI 5-13
REG[3:0] - bit in INIT 3-15
REL - relative addressing mode 11-8
RESET pin 2-3
resets
circuit 2-3
, clock monitor 10-4 10-5
, COP 10-2 10-3
effect on 8-bit modulus timers 10-9
effect on A/D 10-10
effect on COP 10-9
effect on CPU 10-8
effect on I/O 10-8
resets (continued)
effect on LCD module 10-10
effect on memory map 10-8
effect on pulse accumulator 10-9
effect on RTI 10-9
effect on SCI 10-9
effect on SPI 10-10
effect on system 10-10
effect on timer 10-8
effects of 10-7
external 10-2
HPRIO — Highest priority I-bit interrupt and misc. reg.
10-12
power-on, POR 10-1
priorities 10-11
processing flow 10-19
RESET pin 10-2
resetting the COP watchdog 10-3
, RFI 2-4 2-5
RIE - bit in SCCR2 5-9
, RIE2 - bit in S2CR2 5-16 6-10
ROM 3-5
ROMAD - bit in CONFIG 3-12
ROMON - bit in CONFIG 3-14
mask option 3-14
ROW - bit in PPROG 3-26
, RTI 8-2 8-19
PACTL — Pulse accumulator control reg. 8-22
rates 8-19
reset 10-9
TFLG2 — Timer interrupt flag reg. 2 8-21
TMSK2 — Timer interrupt mask reg. 2 8-20
RTIF - bit in TFLG2 8-21
RTII - bit in TMSK2 8-20
RTR[1:0] - bits in PACTL 8-22
, RWU - bit in SCCR2 5-4 5-9
RWU2 - bit in S2CR2 5-16
S
S2B[12:0] - bits in S2BDH/L 6-9
S2BDH, S2BDL — MI BUS clock rate control reg. 6-9
S2BDH, S2BDL — SCI2 baud rate control reg. 5-15
S2CR1 — MI BUS control reg. 1 6-9
S2CR1 — SCI2 control reg. 1 5-16
S2CR2 — MI BUS2 control reg. 2 6-10
S2CR2 — SCI2 control reg. 2 5-16
S2DRH, S2DRL — SCI2 data high/low reg. 5-17
S2DRL — MI BUS2 data reg. 6-12
S2SR1 — MI BUS status reg. 1 6-11
S2SR1 — SCI2 status reg. 1 5-16
S2SR2 — MI BUS2 status reg. 2 6-12
S2SR2 — SCI2 status reg. 2 5-17
S-bit in CCr 11-6
SBK - bit in SCCR2 5-9
, SBK2 - bit in S2CR2 5-16 6-10
SBR[12:0] - bits in SCBDH/L 5-6
SCAN - bit in ADCTL 9-8
SCBDH, SCBDL — SCI baud rate control reg. 5-6
MOTOROLA
x
INDEX
TPG
MC68HC11PH8