MC68HC11PH8 Datasheet, PDF (89/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

4.9
Internal pull-up resistors
Four of the ports (B, F, G and H) have internal, software selectable pull-up resistors under control
of the port pull-up assignment register (PPAR).
4.9.1 PPAR — Port pull-up assignment register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
4
Port pull-up assignment (PPAR) $002C 0
0
0 HWOIF HPPUE GPPUE FPPUE BPPUE 0000 1111
Bits [7:5] — Not implemented; always read zero.
HWOIF — Port H wired-OR interrupt flag
1 (set) – Port H keyboard interrupt request.
0 (clear) – No port H keyboard interrupt request.
This bit is cleared by a write to the PPAR register with HWOIF set. When this function is used,
care must be taken when changing pull-up enable bits to prevent accidental clearing of this flag.
xPPUE — Port x pin pull-up enable
These bits control the on-chip pull-up devices connected to all the pins on I/O ports B, F, G and H.
They are collectively enabled or disabled via the PAREN bit in the CONFIG register (see Section
4.10.2).
1 (set) – Port x pin on-chip pull-up devices enabled.
0 (clear) – Port x pin on-chip pull-up devices disabled.
Note:
FPPUE and BPPUE have no effect in expanded mode since ports F and B are
dedicated address bus or LCD outputs.
Note: When the SCI2 receiver is enabled, the associated pull-up on port G is disabled.
4.10
System configuration
One bit in each of the following registers is directly concerned with the configuration of the I/O
ports. For full details on the other bits in the registers, refer to the appropriate section.
MC68HC11PH8
PARALLEL INPUT/OUTPUT
TPG
MOTOROLA
4-11