MC68HC11PH8 Datasheet, PDF (178/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

9.1.4 Result registers
Four 8-bit registers (ADR1 – ADR4) store conversion results. Each of these registers can be
accessed by the processor in the CPU. The conversion complete flag (CCF) indicates when valid
data is present in the result registers. The result registers are written during a portion of the system
clock cycle when reads do not occur, so there is no conflict.
9.1.5 A/D converter clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock
or an internal RC oscillator for synchronization. When E clock frequency is below 750kHz, charge
leakage in the capacitor array can cause errors, and the internal oscillator should be used. When
the RC clock is used, additional errors can occur because the comparator is sensitive to the
additional system clock noise.
9.1.6 Conversion sequence
A/D converter operations are performed in sequences of four conversions each. A conversion
sequence can repeat continuously or stop after one iteration. The conversion complete flag (CCF)
is set after the fourth conversion in a sequence to show the availability of data in the result
registers. Figure 9-3 shows the timing of a typical sequence. Synchronization is referenced to the
system E clock.
9
E clock
12 cycles
Sample analog input
4 cycles 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc
MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
END
Successive approximation sequence
Convert Þrst
channel and
update ADR1
Convert second
channel and
update ADR2
Convert third
channel and
update ADR3
Convert fourth
channel and
update ADR4
0
32
64
96
128 E clock cycles
Figure 9-3 A/D conversion sequence
MOTOROLA
9-4
ANALOG-TO-DIGITAL CONVERTER
TPG
MC68HC11PH8