MC68HC11PH8 Datasheet, PDF (256/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

M
M - bit in SCCR1 5-8
M2 - bit in S2CR1 5-16
M2DL1:M2DL0 - bits in INIT2 6-8
, , Manchester coding 6-1 6-2 6-3
mask options 1-2
oscillator buffer type 2-4
PLL crystal frequency 2-7
ROMON bit 3-14
security 3-30
stabilization delay timing 3-17
maximum ratings A-1
MBE - bit in EPROG 3-23
MC68HC711PH8 1-1
MCS - bit in PLLCR 2-10
MDA - bit in HPRIO 3-11
memory
corruption of 2-3
– EEPROM 3-25 3-28
, – EPROM 3-5 3-23 3-25
map 3-3
, – mapping 3-4 3-14 3-16
, protection 3-21 3-30
RAM 3-4
RAM stand-by connections 2-13
register map 3-5
ROM 3-5
stretch external access 3-19
memory map, on reset 10-8
, MI BUS 1-2 6-1
block diagram 6-5
, clock rate 6-7 6-9
error detection 6-4
INIT2 — EEPROM mapping and MI BUS delay reg.
6-8
interface 6-6
, Manchester coding 6-1 6-3
pins 6-1
pull field 6-3
push field 6-2
S2BDH, S2BDL — MI BUS clock rate control reg. 6-9
S2CR1 — MI BUS control reg. 1 6-9
S2CR2 — MI BUS2 control reg. 2 6-10
S2DRL — MI BUS2 data reg. 6-12
S2SR1 — MI BUS status reg. 1 6-11
S2SR2 — MI BUS2 status reg. 2 6-12
ST4XCK clock 6-7
timing 6-2
, MIE2 - bit in S2CR1 5-16 6-9
MISO 7-4
MODA/LIR pin 2-13
MODB/VSTBY pin 2-13
MODF - bit in SPSR 7-8
modulus timers - see 8-bit modulus timers
MOSI 7-4
, MSTR - bit in SPCR 7-5 7-6
MULT - bit in ADCTL 9-9
, multiplexer, A/D 9-2 9-7
multiplication factor, PLL 2-11
N
N-bit in CCR 11-5
NF - bit in SCSR1 5-11
, NF2 - bit in S2SR1 5-16 6-12
, NMI 2-12 10-16
NOCOP - bit in CONFIG 10-7
, , , noise 2-2 2-4 2-5 2-7
non-maskable interrupt 2-12
NOSEC - bit in CONFIG 3-31
O
OC1D — Output compare 1 data reg. 8-13
OC1D[7:3] - bits in OC1D 8-13
OC1F–OC4F - bits in TFLG1 8-16
OC1I–OC4I - bits in TMSK1 8-15
OC1M — Output compare 1 mask reg. 8-13
OC1M[7:3] - bits in OC1M 8-13
ODD - bit in PPROG 3-25
OL[2:5] - bits in TCTL1 8-14
OM[2:5] - bits in TCTL1 8-14
operating modes 3-1
baud rates 3-2
bootstrap 3-2
expanded 3-1
HPRIO register 3-11
, selection of 2-13 3-10
single chip 3-1
, STOP 3-5 10-18
test 3-2
VSTBY 3-5
WAIT 10-17
OPT2 — System configuration options reg. 2 3-18
, OPTION — System configuration options reg. 1 9-5 10-4
OR - bit in SCSR1 5-11
, OR2 - bit in S2SR1 5-16 6-11
ordering information B-6
oscillator 2-3
connections 2-4
output compare 8-11
overflow bit in CCR 11-5
P
packages
CERQUAD B-4
options 2-1
PLCC B-3
thermal characteristics A-1
TQFP B-5
PACNT — Pulse accumulator count reg. 8-26
PACTL — Pulse accumulator control reg. 8-25
PAEN - bit in PACTL 8-25
PAIF - bit in TFLG2 8-27
PAII - bit in TMSK2 8-27
PAMOD - bit in PACTL 8-25
MOTOROLA
viii
INDEX
TPG
MC68HC11PH8