MC68HC11PH8 Datasheet, PDF (151/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.4.9 TMSK2 — Timer interrupt mask register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer
prescaler control bits are included in this register.
Note:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the
corresponding interrupt sources.
TOI — Timer overflow interrupt enable
1 (set) – Timer overflow interrupt requested when TOF is set.
0 (clear) – TOF interrupts disabled.
RTII — Real-time interrupt enable (refer to Section 8.1.5)
1 (set) – Real time interrupt requested when RTIF is set.
0 (clear) – Real time interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (refer to Section 8.1.8)
8
PAII — Pulse accumulator input edge interrupt enable (refer to Section 8.1.8)
Bits [3, 2] — Not implemented; always read zero.
PR[1:0] — Timer prescaler select
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can only be
written once, and the write must be within 64 cycles after reset. See Table 8-1 for specific timing
values.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-17