EP2SGX60CF780C4N Datasheet, PDF (98/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

PLLs and Clock Networks
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–61 shows the 12 dedicated CLK
pins driving global clock networks.
Figure 2–61. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Stratix II GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as
shown in Figure 2–62.
2–90
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007